// Copyright (C) 1953-2022 NUDT
// Verilog module name - mbus_parse_and_encapsulate_osm 
// Version: V4.1.0.20221206
// Created:
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//         
///////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps

module mbus_parse_and_encapsulate_osm
(
        i_clk              ,
        i_rst_n            ,

        iv_addr                  ,         
        iv_wdata                 ,         
        i_wr                     ,      
        i_rd                     ,       
        o_wr                     ,      
        ov_addr                  ,      
        ov_rdata                 ,   

		o_slave_port                ,
        
        iv_rxasyncfifo_overflow_cnt ,
        iv_rxasyncfifo_underflow_cnt,
        iv_txasyncfifo_overflow_cnt ,
        iv_txasyncfifo_underflow_cnt
);
// I/O
// i_clk & rst
input                  i_clk;
input                  i_rst_n;

input       [18:0]      iv_addr;                         
input       [31:0]      iv_wdata;                        
input                   i_wr;         
input                   i_rd;         
output reg              o_wr            ;          
output reg  [18:0]      ov_addr         ;       
output reg  [31:0]      ov_rdata        ;

output reg             o_slave_port;
input      [15:0]      iv_rxasyncfifo_overflow_cnt;
input      [15:0]      iv_rxasyncfifo_underflow_cnt;
input      [15:0]      iv_txasyncfifo_overflow_cnt;
input      [15:0]      iv_txasyncfifo_underflow_cnt;
//***************************************************
//               command parse
//***************************************************
always @(posedge i_clk or negedge i_rst_n) begin
    if(i_rst_n == 1'b0)begin       
        o_wr                  <= 1'b0    ;
        ov_addr               <= 19'b0   ;
        ov_rdata              <= 32'b0   ;

        o_slave_port      <= 1'b0;		
    end
    else begin
        if(i_wr)begin       
            if(iv_addr == 19'd0)begin
                o_slave_port      <= iv_wdata[0];
            end
            else begin
                o_slave_port      <= o_slave_port;
            end
        end
        else if(i_rd)begin
            ov_addr      <= iv_addr;
            o_wr         <= 1'b1;
            if(iv_addr == 19'd0)begin
                ov_rdata     <= {31'b0,o_slave_port}; 
            end
            else if(iv_addr == 19'd1)begin
                ov_rdata     <= {iv_rxasyncfifo_underflow_cnt,iv_rxasyncfifo_overflow_cnt};  
            end
            else if(iv_addr == 19'd2)begin
                ov_rdata     <= {iv_txasyncfifo_underflow_cnt,iv_txasyncfifo_overflow_cnt}; 
            end           
            else begin
                ov_rdata     <= 32'hffff_ffff;
            end        
        end
        else begin
            o_wr                  <= 1'b0    ;
            ov_addr               <= 19'b0   ;
            ov_rdata              <= 32'b0   ;  
        end
    end
end    
endmodule
    